An energy saving model for fully associative cache

Fully associative caches expend more energy as the comparison of the address and data parts are done in parallel in all the blocks. This paper proposes a model which reduces energy consumption in fully associative cache. The model assumes an address cache similar to tag cache. The address cache contains the address portion of all the cache blocks. A line is matched with address cache. On hit the corresponding block is enabled for further comparison. On miss the least recently used block is replaced updating the address cache. This model was simulated for SPEC2K benchmarks. An energy saving of 99% is seen with average memory access time improvement of 85% for write through cache.