Multiway netlist partitioning onto FPGA-based board architectures

FPGAs are well accepted as an alternative to ASICs and for rapid prototyping purposes. Netlists of designs which are too large to be implemented on a single FPGA, have to be mapped onto a set of FPGAs, which could be organized on an FPGA board containing various FPGAs connected by interconnection networks. This paper presents an efficient approach to the problem of multiway partitioning of large FPGA netlists onto heterogeneous FPGA boards. To optimize the resulting partitioning with respect to the target architecture, our algorithm is able to consider the board architecture