A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability

This paper presents a design methodology of reconfigurable hybrid carry lookahead/carry select adders (CLSA). A novel partition scheme is used to divide a large hybrid CLSA into multiple small ones with blocking specific inputs of the carry lookahead unit in the hybrid CLSA. The partition scheme incurs no delay penalty regardless of the size of adders. Moreover, the additional area cost is very small. For example, a reconfigurable 16-bit hybrid CLSA with four different partition configurations needs additional 6 two-input AND gates and three two-input multiplexers. Simulation results show that the delay of a 64-bit reconfigurable CLSA is only about 1.38 ns in 0.18 μm technology.