A novel multiplexer based truncated array multiplier

The design of high-speed, area-efficient and low power multiplier is essential for the VLSI implementation of DSP systems. In many applications, like digital filtering, the inputs are contaminated by noise and precise outputs are often not required. It has been shown that the area and power of multiplier can be significantly reduced by truncation techniques at the expense of truncation errors. This paper presents a novel multiplexer based truncated array multiplier, which has leveraged and improved upon three existing truncation algorithms. An exhaustive error analysis was also performed to evaluate the truncation errors of the new truncated multiplier. The proposed truncated multiplier was compared to one implemented with the standard truncation schemes in latency, silicon area and power dissipation. Simulation results have attested the accuracy and VLSI performance ascendancy of the proposed truncated multiplier.