A hardware/software partitioning algorithm for pipelined instruction set processor

Author

Binh, Nguyen Ngoc ; Imai, Masaharu ; Shiomi, Akichika ; Hikichi, Nobuyuki

Author_Institution

Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan

fYear

1995

fDate

18-22 Sep 1995

Firstpage

176

Lastpage

181

Abstract

This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to find a set of HW implemented operations to achieve the highest performance of a pipelined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method is effective and quite efficient

Keywords

circuit optimisation; computer aided software engineering; development systems; instruction sets; logic CAD; logic design; microprocessor chips; pipeline processing; hardware/software partitioning algorithm; pipeline hazards; pipelined instruction set processor; power consumption constraint; Application specific processors; Clocks; Design methodology; Energy consumption; Hardware; Hazards; Partitioning algorithms; Pipeline processing; Registers; Software algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Conference_Location

Brighton

Print_ISBN

0-8186-7156-4

Type

conf

DOI

10.1109/EURDAC.1995.527405

Filename

527405