A global interconnect optimization algorithm under accurate delay model using solution space smoothing

Buffer insertion plays a great role in modern global interconnect optimization, while too many buffers may exhaust routing resources, and result in the rise of power dissipation. In this paper, we introduce solution space smoothing technique to construct routing trees under accurate delay models with consideration of buffer/wire sizing and routing obstacles simultaneously. Experimental result shows, compared with the previous Fast-RTBW algorithm which uses simulated annealing under Elmore delay, our algorithm gives comparable routing tree solutions with about 61% of the total buffer areas that Fast-RTBW uses, and the running time is 5-30 times faster than that of Fast-RTBW.