A sparsified vector potential equivalent circuit model for massively coupled interconnects

The vector potential equivalent circuit (VPEC) model was introduced for accurately modeling inductive interconnects, and the main computation complexity is inverting the full inductance matrix. In this paper, we develop two sparse approximated inversions to extract the sparsified VPEC model without full inductance matrix inversion. One is a heuristic windowing, and the other is the Schur´s windowing, based on the generalized Schur´s interpolation algorithm. Both methods have faster extraction time and higher accuracy compared to the existing truncation-based sparsification, and the Schur´s windowing achieves the best accuracy. Furthermore, the resultant windowed VPEC circuits can be directly simulated in SPICE with orders of magnitude speedup and less than 3% error compared to the full PEEC model.