Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing. We obtain optimal solutions for the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS) under the delay constraints. These solutions can be used to estimate the power dissipation in the interconnect designs.