Title :
A unified approach to the extraction of realistic multiple bridging and break faults
Author :
Spiegel, Gerald ; Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets and faults that break a net into more than two parts. The developed analysis method extracts the complete set of realistic faults from the layout and for each fault computes the probability of occurrence
Keywords :
CMOS logic circuits; circuit layout CAD; fault diagnosis; integrated circuit layout; integrated circuit modelling; logic testing; CMOS AND gate; analysis method; fault model; inductive fault analysis; realistic multiple break faults; realistic multiple bridging faults; spot defects; transistor net list; CMOS technology; Circuit analysis; Circuit faults; Circuit testing; Conductors; Fault tolerance; Insulation; Metal-insulator structures; Probability; Semiconductor device modeling;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527406
