Title :
An energy-efficient charge recycling approach for a SAR converter with capacitive DAC
Author :
Ginsburg, Brian P. ; Chandrakasan, Anantha P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC is presented. By splitting the MSB capacitor into b - 1 binary scaled sub-capacitors, the average switching energy of the array can be reduced by 37% compared to a conventional switching method. A formal solution of the switching energy in four different switching methods is included, and the equations are verified using HSPICE simulations of a 10b capacitor array in a 0.18 μm CMOS process.
Keywords :
CMOS integrated circuits; SPICE; analogue-digital conversion; capacitor switching; circuit simulation; digital-analogue conversion; 0.18 micron; ADC; CMOS process; DAC capacitor array; HSPICE simulations; MSB capacitor; SAR converter; average switching energy; binary scaled sub-capacitors; capacitive DAC; capacitor switching; energy-efficient charge recycling; successive approximation register; Capacitors; Differential equations; Energy efficiency; Logic arrays; Recycling; Shift registers; Switches; Switching converters; Topology; Voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464555
