Tri-gate poly-Si thin-film transistor with nanowire channels

The fine grain structure of poly-Si thin-film transistor (poly-Si TFT) is known to affect the carrier transport and device performance. Various methods have been proposed to increase the grain size of poly-Si thin films, including excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC), in order to improve device characteristics. An alternative approach for minimizing the negative impacts of poly-Si film is to reduce the total amount of defects by thinning down the channel body. In line with this, the adoption of a multiple-gated (MG) nanowire (NW) structure is promising. The MG configuration can further improve the performance of poly-Si TFT devices through enhanced gate controllability over the channel. In this work, we propose a new fabrication scheme for poly-Si NW formation. Poly-Si TFTs with ultra-thin NW channels and tri-gated configuration are demonstrated and characterized. Moreover, a multiple-channel layout scheme is proposed to multiply the device drive current while minimizing the device layout area.