FPGA Implementation of Full Parallel and Pipelined FFT

Author

Xiaobo Zou ; Yunxue Liu ; Yuhui Zhang ; Pengfei Liu ; Fen Li ; Ying Wu

Author_Institution

Sch. of Sci. & Technol. for Opto-Electron. Inf., Yantai Univ., Yantai, China

fYear

2012

fDate

21-23 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

This paper addresses the real-time demand of radix-4 FFT processor in modern digital signal processing domain. Full parallel and pipelined architecture can be a good solution while too much hardware is consumed. Therefore a useful optimization method of complex multiplier and twiddle factor which has been successfully used to implement the FFT algorithms achieving a reduction in multipliers´ usage of up to 38 percent. Furthermore, we also present a useful truncation metric about fixed-point calculation.

Keywords

digital signal processing chips; fast Fourier transforms; field programmable gate arrays; fixed point arithmetic; optimisation; parallel architectures; pipeline arithmetic; FFT processor; FPGA implementation; complex multiplier; digital signal processing; fixed point arithmetic; optimization method; parallel architecture; pipelined architecture; twiddle factor; Algorithm design and analysis; Field programmable gate arrays; Hardware; Indexes; Optimization methods; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing (WiCOM), 2012 8th International Conference on

Conference_Location

Shanghai

ISSN

2161-9646

Print_ISBN

978-1-61284-684-2

Type

conf

DOI

10.1109/WiCOM.2012.6478526

Filename

6478526