FPGA Implementation of High-Throughput Complex Adaptive Equalizer for QAM Receiver

This paper presented an FPGA implementation of high- throughout adaptive equalizer for QAM receiver. The system was designed based on the architecture for adaptive decision feedback equalizer. Constant modulus algorithm was considered for the blind equalization mode which was followed by direct- decision (DD) mode. The feed forwards filter and feedback filter were designed based on FIR filter in the transpose-form which can achieve shorter critical path for hardware design. The whole design, which can achieve the channel equalization for 16-, 32- 64-, 128- and 256-QAM, was implemented under Xilinx Vertex 4 XC4VSX55 FPGA. The maximum clock frequency after routed reached to 128.6MHz. Simulations showed the good performance of this design. By FPGA implementation, the efficiency was proved.