Analog slice turbo decoding

This paper presents the design of an analog turbo decoder for DVB-RCS-like applications using a slice architecture. The constituent decoders for different frame lengths are made up of duplicated elements chosen from a small set of reduced-size MAP decoders. This slicing technique enhances the design of the decoder in terms of simplicity, testability, re-usability and robustness. It is illustrated with the example of a turbo decoder for frames of 48 symbols sliced into two sub-frames. The error correction performance of this analog slice decoder is equal to that of the digital counterpart without slices. Transistor-level simulations show a potential throughput up to 1.5Gb/s for a 2.9mW core power consumption per information bit and per state in a 0.25μm BiCMOS process.