A frequency up-conversion and two-step channel selection embedded CMOS D/A interface

A multi-functional D/A interface for a novel two-step-up wireless transmitter architecture is described. A current-mode analog-double-quadrature sampling (A-DQS) technique is proposed in a two-channel 10-bit 120-MSample/s current steering D/A converter (DAC) to realize not only D/A conversion, but also baseband-to-IF image-reject upconversion, and IF channel selection for simplifying the radio front-end channel selection complexity. Realized with 0.35-μm CMOS in Cadence™, the active die area is 2.55 mm². The integral (INL) and differential (DNL) nonlinearities are better than ±0.42 LSB and ±0.38 LSB, respectively. The spurious-free dynamic range (SFDR) is >56 dB. The power dissipation is 163 mW from 2.5-V analog/1.8-V digital supplies.