DocumentCode :
3541356
Title :
A novel DC-offset cancelling circuit for DCR
Author :
Yan, Jiangnan ; Zheng, Yuanjin ; Xu, Yong Ping
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
396
Abstract :
The paper describes a novel DC-offset canceling structure for a direct-conversion receiver (DCR). The proposed structure uses an I/Q tuning loop to remove DC-offset. The I/Q mismatch issue is discussed and, accordingly, a solution to suppress I/Q mismatch effects is adopted. A variable bandwidth technique is employed to accelerate the loop acquisition when the system is first turned on. Simulation results show that the differential DC-offset voltage is less than 3 mV after the loop becomes locked when a DC-offset of 100 mV is presented. Moreover, the tuning loop can efficiently suppress the effects of I/Q mismatch.
Keywords :
circuit tuning; integrated circuit design; low-pass filters; network analysis; radio receivers; 100 mV; DC-offset cancelling circuit; I/Q mismatch effects suppression; I/Q tuning loop; chip size; circuit analysis; design issues; differential DC-offset voltage; direct-conversion receiver; low pass filter; power consumption; variable bandwidth; Acceleration; Bandwidth; Circuit optimization; Digital signal processing chips; Energy consumption; Frequency; Microelectronics; Signal detection; Switches; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1464608
Filename :
1464608
Link To Document :
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