DocumentCode :
3541366
Title :
An adaptive distributed algorithm for sequential circuit test generation
Author :
Sienicki, James ; Bushnell, Michael ; Agrawal, Prathima ; Agrawal, Vishwani
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear :
1995
fDate :
18-22 Sep 1995
Firstpage :
236
Lastpage :
241
Abstract :
We describe the parallelization of sequential circuit test generation on an Ethernet-connected network of SUN workstations. We use the observations of the previous work to execute the program in two phased. All processors simultaneously ran the test generation program, Gentest. In the first phase, the fault list is equally divided among processors, each of which derives tests for targets from its list. A time limit is used to abandon the search for a test for hard to detect faults. Any test found is immediately used to simulate all faults, including those assigned to other processors. Due to the sequential nature of the circuit test vectors are not shared, but the fault simulation data are shared among processors. This phase terminates when only hard to detect faults are left. In the second phase, each remaining fault is simultaneously targeted by all processors, which now have different initial states of the circuit. The first processor to find the test interrupts all others, at which point all processors simultaneously target the next remaining fault. The results show that with this dual strategy, the speedup can be made to increase almost linearly, or sometimes superlinearly, with the number of processors
Keywords :
automatic test software; logic CAD; logic design; logic testing; parallel algorithms; sequential circuits; Ethernet-connected network; Gentest; SUN workstations; adaptive distributed algorithm; circuit test vectors; fault simulation data; parallelization; sequential circuit test generation; test generation program; Circuit faults; Circuit simulation; Circuit testing; Distributed algorithms; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; Sun; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
Type :
conf
DOI :
10.1109/EURDAC.1995.527412
Filename :
527412
Link To Document :
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