A pseudo-differential CMOS receiver insensitive to input common mode level

Author

Kim, Nam-Seog ; Cho, Uk-Rae ; Byun, Hyun-Geun

Author_Institution

Memory Div., Samsung Electron., Kyeonggi-Do, South Korea

fYear

2005

fDate

23-26 May 2005

Firstpage

440

Abstract

In this paper, composite replica-tail-feedback (CRF) bias is proposed to prevent the valid window from reducing due to variations of input common mode (CM) level. The CRF bias is applied to a differential static amplifier and a differential clocked receiver. They are fabricated with a 0.1 μm CMOS process and the supply voltage is 1.2 V. When the input CM level changes between 0.5 V and 1.0 V, the static amplifier features output CM level variations of ±2.3% and propagation delay variations of ±7.5% against each average. Under the same condition, the clocked receiver provides zero setup and 60 ps hold, and the alterations of hold are 14 ps.

Keywords

CMOS integrated circuits; differential amplifiers; low-power electronics; receivers; 0.1 micron; 0.5 to 1.0 V; 1.2 V; 60 ps; composite replica-tail-feedback bias; differential clocked receiver; differential static amplifier; input common mode level insensitive receiver; low power chip-to-chip interface; output CM level variations; propagation delay variations; pseudo differential signal interface; pseudo-differential CMOS receiver; CMOS process; Clocks; Design engineering; Differential amplifiers; Frequency; Low-frequency noise; MOSFET circuits; Propagation delay; Random access memory; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464619

Filename

1464619