DocumentCode :
3541443
Title :
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
Author :
Hua, Chung-Hsien ; Hwang, Wei ; Chen, Chih-Kai
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
444
Abstract :
A noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional keepers. The conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fan-in dynamic circuits are used to demonstrate the effectiveness of the conditional keeper on noise immunity. Distributed power gating combined with clock gating design is also examined. All the simulation results are based on TSMC 100 nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% power reduction and 20% delay reduction are achieved. Under the same delay criteria, more than 1.25× noise immunity improvement is attained.
Keywords :
CMOS logic circuits; integrated circuit noise; interference suppression; logic circuits; 100 nm; CMOS; clock gating; control signal timing effects; delay reduction; distributed power gating; high fan-in dynamic circuits; noise immunity; noise-tolerant XOR-based conditional keeper; power reduction; unity-gain DC noise criteria; CMOS technology; Circuit noise; Clocks; Coupling circuits; Delay; Energy consumption; Leakage current; Multiplexing; Noise figure; Noise reduction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1464620
Filename :
1464620
Link To Document :
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