DocumentCode :
3541510
Title :
Fixed sign Walsh transform and its iterative hardware architecture
Author :
Falkowski, Bogdan J. ; Yan, Shixing
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
484
Abstract :
The paper describes an efficient way of implementing the hardware of a sign Walsh transform. Such a nonlinear transforms convert binary/ternary vectors into the spectral domain and is important in many signal processing applications including CDMA coding and the analysis of logic design. The approach used here is based on fixed butterfly diagrams that can be easily implemented in hardware.
Keywords :
Walsh functions; hypercube networks; iterative methods; logic design; signal processing; spectral analysis; transforms; vectors; CDMA coding; Walsh functions; binary vectors; fixed butterfly diagrams; fixed sign Walsh transform; logic design analysis; logic functions; nonlinear transform; sign transform; signal processing; spectral domain; ternary vectors; Application software; Computer applications; Hardware; Logic design; Logic functions; Multiaccess communication; Multivalued logic; Signal analysis; Signal processing; Signal synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1464630
Filename :
1464630
Link To Document :
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