Study of low frequency noise behavior in silicon nanowire transistors fabricated with top-to-down approach

LFN in nSNWTs realized with top-to-down process is studied and analyzed in this paper. Correlated-mobility fluctuation model can explain the LFN behavior at low drain current, while significant noise enhancement is observed at high current region due to the impact of parasitic resistance of the ultra-narrow SDE regions in the nanowire transistors. Design optimizations to reduce the resistance impact on LFN are necessary in SNWTs for analog/RF applications. In addition, significant noise dispersion up to 5 orders magnitude is observed and its gate bias dependence is discussed. This variation challenges the modeling and design of the noise sensitive circuits. The extracted N_ot, is higher than conventional SiO₂/poly-silicon gate stack, which may be attributed to the gate-all-around ultra-small nanowire structure with various orientations of the channel surface.