A high performance architecture of EBCOT encoder in JPEG 2000

Author

Xiaolang, Yan ; Qin Ying ; Ye, Yang ; Haitong, Ge

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China

fYear

2005

fDate

23-26 May 2005

Firstpage

492

Abstract

A high performance architecture for EBCOT in JPEG 2000 is proposed. The architecture consists of a column-and-pass dual parallel context modeling unit capable of the simultaneous processing of four samples, and a pipelined binary arithmetic coder based on a two-context window running at double the clock frequency to match the processing rate of the context modeling unit. Simulation results show that this design reduces processing time by about 60% compared with existing pass-parallel architectures and is able to process a 512×512 grayscale image in approximately 4 ms at 100 MHz system clock rate.

Keywords

block codes; data compression; image coding; parallel processing; pipeline arithmetic; 100 MHz; 262144 pixel; 512 pixel; EBCOT encoder; JPEG 2000; clock frequency; column-and-pass modeling unit; context modeling unit; dual parallel modeling unit; embedded block coding; grayscale image; optimized truncation; pass-parallel architectures; pipelined binary arithmetic coder; Acceleration; Arithmetic; Clocks; Computer architecture; Context modeling; Frequency; Hardware; Parallel processing; Process design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464632

Filename

1464632