An experimental study of TiN gate FinFET SRAM with (111)-oriented sidewall channels

Author

Liu, Y.X. ; Hayashida, T. ; Matsukawa, T. ; Endo, K. ; O´uchi, S. ; Sakamoto, K. ; Masahara, M. ; Ishii, K. ; Tsukada, J. ; Ishikawa, Y. ; Yamauchi, H. ; Ogura, A. ; Suzuki, E.

Author_Institution

Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan

fYear

2008

fDate

15-16 June 2008

Firstpage

1

Lastpage

2

Abstract

TiN gate FinFET SRAM half-cells with different ÃŸ-ratios from 1-3 have successfully been fabricated by using the orientation dependent wet etching and conventional reactive sputtering, for the first time. It is experimentally found that static noise margin (SNM)at read condition increases with increasing ÃŸ-ratio due to the strength of pull-down transistor. To overcome SRAM cell size increment with increasing ÃŸ, a fin-height controlled pass-gate (PG) SRAM structure is proposed.

Keywords

MOSFET; SRAM chips; sputter etching; titanium compounds; transistors; SRAM cell size increment; gate FinFET SRAM; orientation dependent wet etching; oriented sidewall channels; pass-gate SRAM structure; pull-down transistor; reactive sputtering; static noise margin; Circuits; Design optimization; Fabrication; FinFETs; MOS devices; Random access memory; Size control; Sputtering; Tin; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-2071-1

Type

conf

DOI

10.1109/SNW.2008.5418473

Filename

5418473