Synthesis of reconfigurable multiplier blocks: part - II algorithm

Reconfigurable multiplier blocks (ReMB) offer significant area, delay and possibly power reduction in time-multiplexed implementation of multiple constant multiplications. This paper and its companion paper (entitled part I - fundamentals) together present a systematic synthesis method for single input single output (SISO) and single input multiple output (SIMO) ReMB designs. This paper illustrates the synthesis method through examples. The companion paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The proposed method achieves reduced logic-depth and area over standard multipliers/multiplier blocks.