• DocumentCode
    3541660
  • Title

    Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

  • Author

    Yu, Shimeng ; Zhao, Yuning ; Song, Yuncheng ; Gang Du ; Kang, Jinfeng ; Han, Ruqi ; Liu, Xiaoyan

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • fYear
    2008
  • fDate
    15-16 June 2008
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.
  • Keywords
    MOSFET; statistical analysis; 3D simulation; FinFET; autocorrelation function calculation; gate line edge roughness impact; leakage current; sub-threshold slope; threshold voltage; various root mean square amplitude; Autocorrelation; FinFETs; Fluctuations; Leakage current; MOSFETs; Microelectronics; Random sequences; Root mean square; Solid modeling; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-2071-1
  • Type

    conf

  • DOI
    10.1109/SNW.2008.5418481
  • Filename
    5418481
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3541660