Finger number and width variation effect of nano-scale strained NMOS device with and without protection diode

The enhancement of carrier mobility by strain is necessary to improve transistor performance with scaling down. Especially the technique of inducing strain by using a tensile or compressive nitride capping layer is more attractive because of its relative process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETS. Also to improve the packing density of integrated circuits, scaling down of isolation region is necessary. Shallow Trench Isolation (STI) is usually used in order to avoid the subthreshold hump, bird´s beak and field oxide thinning effect in LOCOS. Compared with LOCOS isolation, STI has various additional advantages such as perfect surface planarity, scalability and latchup immunity, However the reliability of strained NMOS device with narrow width and gate finger number variation at 60nm gate length has not been investigated yet in detail and also protection diode effect. In this work, we have shown various STI stress and protection diode effects in narrow width device, finger number variation of the gate with 60nm gate length technology by HCE (Hot Carrier Effect), 1/f noise.