Title :
Low-leakage repeaters for NoC interconnects
Author :
Morgenshtein, Arkadiy ; Cidon, Israel ; Kolodny, Avinoam ; Ginosar, Ran
Author_Institution :
Electr. Eng. Dept., Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
Several low-leakage repeater circuits for network-on-chip (NoC) interconnects are presented and analyzed for various utilization rates. The recently proposed staggered-Vt (SVT) repeater is compared with the novel dual-Vt domino (DTD) repeaters and sleep repeaters (SR). These circuits are compared with standard low-Vt (LVT) repeaters in a 32-bit link. Up to 70% and 61% power reduction was obtained in SVT and DTD repeaters, respectively. DTD repeaters are the most area-efficient ones, showing 40% reduction in total area of repeaters. Sleep repeaters are most area-consuming and less effective in high and moderate utilization rates, but comparable to SVT in terms of power for utilization rates below 2%, showing 72% power reduction.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit technology; leakage currents; nanoelectronics; repeaters; system-on-chip; SoC; area efficiency; dual threshold voltage domino repeaters; dual-Vt domino repeaters; leakage current; low threshold voltage repeaters; low-Vt repeaters; low-leakage repeater circuits; nanometer CMOS circuits; network design; network-on-chip interconnects; power reduction; sleep repeaters; staggered threshold voltage repeaters; staggered-Vt repeater; system-on-chip; CMOS technology; Design optimization; Integrated circuit interconnections; Inverters; Minimization; Network-on-a-chip; Power system interconnection; Repeaters; Timing; Wire;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464659
