Non-interleaving architecture for hardware implementation of modular multiplication

Global interconnect is a key potential bottleneck to advancing the performance of high-speed integrated circuits, especially for the large bit modular multiplier used in RSA systems. Architectural approaches to hardware implementation of RSA are presented. Specially, we extend the recently proposed distributed module cluster (DMC) microarchitecture to reduce the long latency in calculating modular exponentiation. In the non-interleaving architecture, so-called NI-DMC, the bubble in the pipeline is eliminated by using longer processing cells and bringing forward certain critical signals. Experimental results show that the new approach significantly exceeds the DMC-based approach in performance, with a relatively small increase in area overhead.