Title :
Computing subsets of equivalence classes for large FSMs
Author :
Cabodi, Gianpiero ; Quer, Stefano ; Camurati, Paolo
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
Computing equivalence classes for FSMs has several applications to synthesis and verification problems. Symbolic traversal techniques are applicable to medium-small circuits. This paper extends their use to large FSMs by means of cofactor-based enhancements to the state-of-the-art approaches and of underestimations of equivalence classes. The key to success is pruning the search space by constraining it. Experimental results on some of the larger ISCAS´89 and MCNC circuits show its applicability
Keywords :
equivalence classes; finite state machines; logic CAD; logic design; cofactor-based enhancements; equivalence classes; symbolic traversal techniques; synthesis; verification; Automata; Boolean functions; Circuit synthesis; Data structures; Formal verification; Graph theory; Latches; Minimization; Space exploration; State-space methods;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527419