Area and power reduction techniques for time-based image sensor pixel design

This paper presents analytical considerations and practical thoughts leading to the design and implementation of a low power, small-area voltage comparator for pixel-level signal processing in time-based image sensors. The circuit is based on a standard two-stage operational amplifier topology and features an offset suppression technique to minimize the area requirements, a tunable hysteresis and a novel dynamic current control scheme to reduce power consumption. The circuit has been implemented in a QVGA asynchronous pixel array, fabricated in standard 0.18¿m CMOS process. We present the circuit concept and design considerations aiming at minimum power consumption and silicon area. Measurements from the fabricated chip are shown and compared to results from theoretical groundwork.