Aspect-based ABV for SystemC transaction level models

Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. No modifications are needed in the design´s SystemC code. Functional as well as performance properties are addressed. We demonstrate the effectiveness of our approach on TLM 2.0 standard compliant models.