Design of a 5-bit 2Gsps CMOS D/A converter for DS-CDMA UWB transceivers

This paper presents a design of a 5-bit 2Gsamples/s digital-to-analog converter (DAC) in 90-nm CMOS technology for DS-CDMA UWB transceivers applications. The proposed DAC was designed with a current binary weighted architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is ±0.002LSB and the measured differential nonlinearity (DNL) is ± 0.015LSB. The DAC implemented in a 90-nm CMOS technology shows spurious free dynamic range (SFDR) of 30dB at Fsignal 500Mhz. The layout occupies a small active area of 62.415um × 38.64um in CMOS 90nm, and the DAC consumes only 38.4 mW of power.