Design of a 5-bit 2Gsps CMOS D/A converter for DS-CDMA UWB transceivers

Author

El khadiri, Karim ; Qjidaa, Hassan

Author_Institution

Fac. des Sci. Dhar El-Mehraz, Lab. d´´Electron. Signaux, Syst. et Inf.(LESSI), Univ. Sidi Mohamed Ben Abdallah, Fes, Morocco

fYear

2012

fDate

10-12 May 2012

Firstpage

1087

Lastpage

1090

Abstract

This paper presents a design of a 5-bit 2Gsamples/s digital-to-analog converter (DAC) in 90-nm CMOS technology for DS-CDMA UWB transceivers applications. The proposed DAC was designed with a current binary weighted architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is ±0.002LSB and the measured differential nonlinearity (DNL) is ± 0.015LSB. The DAC implemented in a 90-nm CMOS technology shows spurious free dynamic range (SFDR) of 30dB at Fsignal 500Mhz. The layout occupies a small active area of 62.415um × 38.64um in CMOS 90nm, and the DAC consumes only 38.4 mW of power.

Keywords

CMOS integrated circuits; code division multiple access; digital-analogue conversion; radio transceivers; ultra wideband communication; CMOS D/A converter; DS-CDMA UWB transceivers; current binary weighted architecture; current sources; differential nonlinearity; digital-to-analog converter; frequency 500 MHz; high frequency sampling rate; integral nonlinearity; optimized deglitch circuit; power 38.4 mW; size 90 nm; word length 5 bit; Artificial intelligence; CMOS integrated circuits; Computer architecture; Manganese; Presses; DS-CDMA; UWB; binary-weighted; digital-to-analog converter (DAC);

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia Computing and Systems (ICMCS), 2012 International Conference on

Conference_Location

Tangier

Print_ISBN

978-1-4673-1518-0

Type

conf

DOI

10.1109/ICMCS.2012.6320140

Filename

6320140