Title :
Processing APL properties to generate verification-ready MDG model
Author :
Hussain, Kamran ; Mohamed, O. Ait ; Abed, Sa Ed
Author_Institution :
Electr. & Comput. Eng. Dept., Concordia Univ., Montreal, QC, Canada
Abstract :
Multiway Decision Graphs (MDGs) are special decision diagrams that subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of datapath circuits. In this paper we propose a new specification language, Abstract Property Language (APL), for the MDG model-checker. The APL language eradicates the restrictions present in the existing LMDG specification language and introduces new operators to improve expressiveness. The paper also presents the design of a front-end translator that accepts specification in APL and builds composite MDG model with the specification directly embedded into its MDG-HDL representation. Finally, some experimental results are presented to show the performance of the APL-Tool and the analysis of the generated code executed on benchmark properties.
Keywords :
binary decision diagrams; formal verification; graph theory; program interpreters; specification languages; MDG-HDL; abstract property language; binary decision diagrams; datapath circuit checking; decision diagrams; front-end translator; multiway decision graphs; specification language; verification-ready MDG model checker; Boolean functions; Circuits; Data engineering; Data structures; Field programmable gate arrays; Hardware; Logic; Monitoring; Specification languages; State-space methods;
Conference_Titel :
Microelectronics (ICM), 2009 International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-5814-1
DOI :
10.1109/ICM.2009.5418635