Title :
Adaptive decision-feedback equalization for band-limited high-speed serial links
Author :
Neurohr, N. ; Schoebinger, M. ; Prete, E. ; Sanders, A.
Author_Institution :
Infineon Technol. AG, Munich, Germany
Abstract :
A high-speed I/O cell comprising a mixed-signal 8-tap decision-feedback equalizer (DFE) with direct cancellation of the first post-cursor intersymbol interference (ISI) has been implemented in 0.13-μm CMOS technology. Based on a joint optimization of algorithms and architecture, a low-complexity architecture has been chosen with respect to a compromise between ISI reduction and implementation complexity. The I/O cell dissipates only 86 mW at the target rate of 6.4 Gbps. It is the core of a high-speed I/O link with adaptive receiver equalization. Due to the residual ISI, the adaptation algorithm has to be modified. The concept has been analyzed by system simulations and verified by measurements of the implemented I/O link.
Keywords :
CMOS integrated circuits; adaptive equalisers; computational complexity; decision feedback equalisers; hardware-software codesign; integrated circuit design; interference suppression; intersymbol interference; mixed analogue-digital integrated circuits; optimisation; 0.13 micron; 6.4 Gbit/s; 86 mW; DFE; ISI reduction; adaptive decision-feedback equalization; adaptive equalization; adaptive receiver equalization; band-limited high-speed serial links; direct ISI cancellation; direct intersymbol interference cancellation; high-speed I/O cell; high-speed I/O link; joint optimization; low-complexity architecture; Additive white noise; Backplanes; CMOS technology; Circuit noise; Crosstalk; Decision feedback equalizers; Frequency; Gaussian noise; Intersymbol interference; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464740
