DocumentCode :
3542282
Title :
An efficient Full-and-Elimination approach for floorplan area minimization
Author :
Wang, Chien-Yen ; Luo, Chaomin ; Jan, Gene Eu
Author_Institution :
Grad. Inst. of Electr. Eng., Nat. Taipei Univ., Taipei, Taiwan
fYear :
2009
fDate :
19-22 Dec. 2009
Firstpage :
244
Lastpage :
247
Abstract :
A new and efficient heuristic methodology, called Full-and-Elimination (FAE), is proposed to solve the floorplan area minimization problem. This approach is inspired by the game, Tetris´. The modules are selected one at a time and placed to the partial floorplan, while attempting to grow on upper, in a row-by-row manner, until all the modules are arranged to the floorplan. In each row, modules are tried to be placed without deadspace. If any row is filled up, this row is viewed as ¿full¿ and thus it is ¿eliminated¿. The modules are sorted and constructively moved into the partial floorplan. A contour that encloses the top of the packed modules in the floorplan is constructed to help for arrangement of the modules. Experimental results on MCNC and GSRC benchmarks demonstrate that we obtain significant improvements on the area minimization and computational efforts. Particularly, our methodology provides greater improvement over other floorplanners as the number of modules increases, which is a feature of scalability.
Keywords :
VLSI; integrated circuit layout; minimisation; GSRC; MCNC; floorplan area minimization; full-and-elimination approach; heuristic methodology; row-by-row manner; Application specific integrated circuits; Chaos; Computational modeling; Explosives; Large-scale systems; Microelectronics; Minimization methods; Runtime; Scalability; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2009 International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-5814-1
Type :
conf
DOI :
10.1109/ICM.2009.5418639
Filename :
5418639
Link To Document :
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