An FPGA implementation of the NTRUEncrypt cryptosystem

The NTRU encryption algorithm, also known as NTRUEncrypt, is a parameterized family of lattice-based public key cryptosystems. Both the encryption and decryption operations in NTRU are based on simple polynomial multiplication which makes it very fast compared to other alternatives such as RSA, and elliptic-curve-based systems. Recently, the NTRU system has been accepted to the IEEE P1363 standards under the specifications for lattice-based public-key cryptography (IEEE P1363.1). In this paper, we investigate several hardware implementation options for the NTRU encryption algorithm. In particular, by utilizing the statistical properties of the distance between the non-zero elements in the polynomials involved in the encryption and decryption operations, we present an architecture that offers different area-speed trade-off and analyze its performance. A prototype for the proposed design is implemented using the virtex-E xcv1600e-8-fg860 FPGA chip.