DocumentCode :
3542376
Title :
FPGA-implementation of a sequential adaptive noise canceller using Xilinx System Generator
Author :
Bahoura, Mohammed ; Ezzaidi, Hassan
Author_Institution :
Dept. of Eng., Univ. of Quebec at Rimouski, Rimouski, QC, Canada
fYear :
2009
fDate :
19-22 Dec. 2009
Firstpage :
213
Lastpage :
216
Abstract :
This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx system generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.
Keywords :
adaptive filters; electrocardiography; field programmable gate arrays; interference (signal); least mean squares methods; pipeline processing; ECG signals; FPGA; MIT-BIH database; XUP Virtex-II Pro development board; Xilinx system generator; electrocardiogram; filter lengths; pipelined LMS-based adaptive noise cancellation; power-line interference; sequential adaptive noise canceller; sequential architecture; Adaptive filters; Delay; Electrocardiography; Field programmable gate arrays; Hardware design languages; Interference; Iterative algorithms; Least squares approximation; Noise cancellation; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2009 International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-5814-1
Type :
conf
DOI :
10.1109/ICM.2009.5418650
Filename :
5418650
Link To Document :
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