CMOS phase frequency detector for high speed applications

Author

Ismail, Nesreen M H ; Othman, Masuri

Author_Institution

Inst. of MicroEngineering & Nanoelectron., Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia

fYear

2009

fDate

19-22 Dec. 2009

Firstpage

201

Lastpage

204

Abstract

A simple new phase frequency detector design is presented in this paper. Falling-Edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18 Â¿m CMOS Process. It consumes 6.6 Â¿W when operating at 50 MHz clock frequency with 1.8 V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.

Keywords

CMOS integrated circuits; charge pump circuits; phase detectors; phase locked loops; power consumption; CMOS phase frequency detector; Silterra CMOS process; charge pump; clock frequency; falling-edge PFD; free dead zone; frequency 50 MHz; high speed applications; low power consumption; phase locked loop; power 6.6 muW; transistors; voltage 1.8 V; Charge pumps; Circuits; Clocks; Energy consumption; Frequency conversion; Nanoelectronics; Phase frequency detector; Phase locked loops; Switches; Voltage-controlled oscillators; Charge Pump; High Speed Integrated Circuits; Phase Locked Loop; Phase frequency Detector;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics (ICM), 2009 International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-5814-1

Type

conf

DOI

10.1109/ICM.2009.5418651

Filename

5418651