A memory-reduced log-MAP kernel for turbo decoder

Generally, the log-MAP kernel of the turbo decoding consumes large memories in hardware implementation. In this paper, we propose a new log-MAP kernel to reduce memory usage. The comparison result shows our proposed architecture can reduce the memory size to 26% of the classical architecture. We also simplify the memory data access in this kernel design without extra address generators. For the 3GPP standard, a prototyping chip of the turbo decoder is implemented to verify the proposed memory-reduced log-MAP kernel in 3.04×3.04mm² core area in the UMC 0.18 μm CMOS process.