Hardware efficient design of speed optimized power stringent Application Specific Processor

New standards in communication, multimedia and signal processing have challenged the researchers to formalize the design methodology of an optimized application specific processor (ASP) where the performance requirement should meet operational constraints like speed, chip area and power consumption. In this paper we describe a novel design approach to design a hardware efficient speed optimized power stringent application specific processor customized for a desired high performance. We initiate the design approach with the mathematical model of the application with strict operating constraints as specifications and finally describe our design at register transfer level. The proposed approach is capable for designing an ASP which is efficient not only in terms of hardware area but also contradictory parameters like speed and power consumption. To demonstrate our design approach for this power limited speed optimized ASP we selected a sample function as our application.