A new low-power turbo decoder using HDA-DHDD stopping iteration

In this paper, we present a new VLSI architecture for a low-power turbo decoder. First, we develop a new soft-in-soft-out decoder architecture and change the sliding window operating flow without attaching LIFO memory. Moreover, we propose a new stopping iteration algorithm that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channels. Experiments show that our architecture gets 25.3%∼39.8% memory size saving in our SISO decoder architecture and one window saving of decoding delay in comparison with the traditional decoder.