DocumentCode
3542519
Title
Improved method to increase AES system speed
Author
Wang, Dazhong ; Li, Xiaoni
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. of Sheffield, Sheffield, UK
fYear
2009
fDate
16-19 Aug. 2009
Firstpage
17958
Lastpage
19054
Abstract
This paper will present the design, implementation and performance of a FIPS - approved cryptographic algorithm - Advanced Encryption Standard (AES), which can be used to protect electronic data. This system consists of two main components: cipher and key-expansion. Furthermore, there are four small parts in process of cipher: subbytes and its inverse, shiftrows and its inverse, mixcolumns and its inverse, and addroundkey and its inverse. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. Moreover, several methods that can increase the running speed constructed in the system will be introduced.
Keywords
cryptography; software standards; AES system speed; Advanced Encryption Standard; cryptographic algorithm; decipher; electronic data protection; key-expansion; symmetric block cipher; Algorithm design and analysis; Arithmetic; Communication standards; Cryptography; Electric variables measurement; Information systems; Instruments; Protection; Standards development; Velocity measurement; AddRoundKey; Advanced Encryption Standard (AES); MixColumns; SubBytes:ShiftRows; decryption; encryption; inverse;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Measurement & Instruments, 2009. ICEMI '09. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-3863-1
Electronic_ISBN
978-1-4244-3864-8
Type
conf
DOI
10.1109/ICEMI.2009.5274272
Filename
5274272
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