A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

In this paper, a high-speed, scalable on-chip serial communication interface design is proposed. The serial communication clock frequency is designed to work correctly at 2.54GHz to provide 2Gbit/s transmission bandwidth for SoC applications. By using the dynamic control technology, we can generate a fast and reliable control signal to activate and stop the oscillation of the ring oscillator. By using the single-phase pulse-triggered TSPC shift register design, we can provide wider timing constraint tolerant range to achieve high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al. (2003)).