A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O

The gate voltage-induced current crowding (GVICC) effect (Lee, J.H., et al., IRPS Proc., p.269-76, 2003) has been found to be the root cause of the failure of the high voltage tolerant I/O (HVT I/O) at a low-voltage ESD event. Based on this finding, a new pre-driver design is proposed to pull down the voltages of the top gate and the bottom gate of the cascode NMOS to 0 V during an ESD zapping event in order to eliminate the GVICC effect. The new pre-driver design can improve the ESD performance of the fully silicided HVT I/O from 500 V to 5 kV during HBM ESD zapping.