A methodology for partitioning DSP applications in hybrid reconfigurable systems

In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different granularity. A hybrid granularity reconfigurable generic system architecture is considered for this methodology, so as the methodology is applicable to a large number of hybrid reconfigurable architectures. For evaluating the effectiveness of the partitioning methodology, a prototype framework has been developed. In the case of the coarse-grain reconfigurable fabric, we consider our developed high-performance coarse-grain data-path. In the experimental results, a maximum clock cycle decrease of 82% relative to the all fine-grain mapping solution is achieved and the overall timing constraints of the application are met.