Title :
An all-digital pulsewidth control loop
Author :
Wang, Yi-Ming ; Hu, Chang-Fen ; Chen, Yi-Jen ; Wang, Jinn-Shyan
Author_Institution :
Dept. of Electr. Eng., Chung-Cheng Univ., Chia-Yi, Taiwan
Abstract :
An all-digital pulsewidth control loop (ADPWCL) is presented. Compared to conventional analog pulsewidth control loops (PWCLs), the ADPWCL is easier to design, more stable, and more suitable to be used as an intellectual property (IP) because the desired duty cycle can be changed in the field. An experimental 0.25-μm ADPWCL has been designed and implemented. The duty cycle can be programmed from 20% to 80% with a step of 10% increment. When operated at 300 MHz and 2 V, the measured duty cycle has only a deviation of 0.4% to 0.7% with a jitter of only 33.3 ps.
Keywords :
comparators (circuits); delay lines; digital control; pulse generators; timing jitter; 0.25 micron; 2 V; 300 MHz; ADPWCL; all-digital pulsewidth control loop; digital pulsewidth converter; digitally controlled delay line; duty cycle deviation; intellectual property; jitter; programmable duty cycle; pulsewidth comparator; CMOS logic circuits; Clocks; Delay lines; Digital control; Intellectual property; Logic gates; MOS devices; Pulse circuits; Signal design; Space vector pulse width modulation;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464823
