An intra prediction pipeline architecture design for AVS encoder

In this paper, an efficient pipelining method to reduce the data dependence for intra prediction in AVS high-definition real-time encoder is proposed. Taking advantage of different data dependences of different locations and prediction modes of sub-blocks within a MB, a new processing order for sub-blocks and their prediction modes is applied in intra prediction pipelining method. The proposed method was implemented in Verilog and synthesized on Xilinx LX330. The simulation result shows that the design is capable of achieving real-time encoding 720p high-definition video sequences at 30 frames per second.