Calibration method of teradyne J750 SOC test system

Author

Wang, Han ; Zhao, Zhao ; Xing, Rongxin ; Li, Jie

Author_Institution

China Electron. Standardization Inst., Beijing, China

fYear

2009

fDate

16-19 Aug. 2009

Abstract

The Teradyne model J750 System on Chip (SOC) test system is one of the most important Integrated Circuit(IC) test systems and used widely in the semiconductor manufacture. The J750 is a 512 or 1024 channel test system, contained entirely in the test head. It is difficult to find if the accuracy of J750 is controlled during the maximum permissible error, since the function and the structure of J750 is complicated and the specification of J750 includes many parameters. In this paper, a calibration method of J750 SOC test system described here resolved the traceability problem of J750, and it is also a recommended calibration method of other SOC test system, such as Teradyne Flex, Verigy 93K, Credence Sapphire, etc.

Keywords

calibration; integrated circuit testing; system-on-chip; Credence Sapphire; Teradyne Flex; Teradyne model J750; Verigy 93K; calibration method; integrated circuit test system; system on chip test system; traceability problem; Calibration; Circuit testing; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit testing; Semiconductor device manufacture; Semiconductor device testing; System testing; System-on-a-chip; Virtual manufacturing; SOC test system; calibration method; traceability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Measurement & Instruments, 2009. ICEMI '09. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3863-1

Electronic_ISBN

978-1-4244-3864-8

Type

conf

DOI

10.1109/ICEMI.2009.5274317

Filename

5274317