Title :
Wiring area optimization in floorplan-aware hierarchical power grids
Author :
Yan, Jin-Tai ; Wu, Chia-Wei ; Chen, Yen-Hsiang
Author_Institution :
Dept. of Comput. Sci. & Inf., Chung-Hua Univ., Hsinchu, Taiwan
Abstract :
In this paper, the floorplan-aware topology of hierarchical power quad-grids is proposed to dynamically meet the local requirement of high current densities inside the floorplan and an iterative linear voltage/current scaling (ILVCS) approach is proposed to meet the current electromigration and voltage IR-drop constraints phase by phase. The experimental results show that our proposed ILVCS approach based on hierarchical power quad-grids can obtain 23%∼44% improvement on total wiring area than the power grids by the wire sizing method for the tested examples.
Keywords :
VLSI; circuit optimisation; electromigration; integrated circuit layout; network topology; wiring; current densities; electromigration; floorplan-aware hierarchical power grids; iterative linear voltage/current scaling; quad-grids; topology; voltage IR-drop constraints; wiring area optimization; Circuits; Computer science; Electromigration; Network topology; Power engineering and energy; Power grids; Very large scale integration; Voltage; Wire; Wiring;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464850
