A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals

This paper describes a test-based digital self-calibration algorithm for high-resolution ADC. The algorithm uses low-linearity signals, small number of memory cells, and simple computations in code-density test to characterize an ADC´s nonlinearity, determines corresponding correction codes, and digitally calibrates the ADC´s output. Simulation results show that INL_k´s of a 16-bit ADC can be tested to 1-LSB accuracy by using 7-bit linear ramp signals and 256 histogram counts. Linearity of the ADC can be improved from 12-bit to 14-bit by using 256 correction codes. The proposed algorithm provides a promising solution to on-chip calibration of high-speed high-precision ADC.